International Conferences

[C33] De Rose R, Carangelo G,  Lanuzza M,  Crupi F,  Finocchio G, Carpentieri M (2017). Impact of voltage scaling on STT-MRAMs through a variability-aware simulation framework. In: 2017 14th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), Giardini Naxos – Taormina, Italy, 12-15 June 2017, pp. 1-4, doi: 10.1109/SMACD.2017.7981583

[C32] Settino F, Lanuzza M, Strangio S, Crupi F,  Palestri P, Esseni D (2017). A virtual III-V tunnel FET technology platform for ultra-low voltage comparators and level shifters. In: 2017 13th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME), Giardini Naxos – Taormina, Italy, 12-15 June 2017, pp. 145-148, doi:  10.1109/PRIME.2017.7974128

[C31] Crupi F, Strangio S, Palestri P, Lanuzza M, Esseni D (2016). Early Assessment of Tunnel-FET for Energy-Efficient Logic Circuits. In: 2016 IEEE 13th International Conference  on Solid-State and Integrated Circuit Technology (ICSIT), Hangzhou, China, 25-28 Oct. 2016,  pp. 27 – 30, doi: 10.1109/ICSICT.2016.7998830, (INVITED)

[C30] Taco R, Levi I, Lanuzza M, Fish A (2016). Extended Exploration of Low Granularity Back Biasing Control in 28nm UTBB FD-SOI Technology. In: 2016 IEEE International Symposium on Circuits and Systems (ISCAS),  Montreal, Canada, 22-25 May 2016, pp. 41-44, doi: 10.1109/ISCAS.2016.7527165

[C29] Strangio S, Palestri P, Lanuzza M, Esseni D, Crupi F, Selmi L (2016). Benchmarks of a III-V TFET technology platform against the 10-nm CMOS technology node considering 28T Full-Adders. In: 2016 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS), Vienna, Austria, 25-27 Jan. 2016, pp. 139 – 142, doi: 10.1109/ULIS.2016.7440072 

[C28] Taco R, Levi I, Lanuzza M, Fish A (2015). Low voltage Ripple Carry Adder with low-Granularity Dynamic Forward Back-Biasing in 28 nm UTBB FD-SOI. In: IEEE SOI-3D-Subthreshold (S3S) Microelectronics Technology Unified Conference, San Francisco (CA), USA, 5-8 Oct. 2015,  pp. 1-2, doi: 10.1109/S3S.2015.7333515

[C27] Cordopatri A, De Rose R, Felicetti C, Lanuzza M, Cocorullo G (2015). Hardware implementation of a Test Lab for Smart Home environments. In: 2015 AEIT International Annual Conference, Naples, Italy, 14-16 Oct. 2015, pp. 16, doi: 10.1109/AEIT.2015.7415221

[C26] Crupi F, Albano D, Lanuzza M (2015). Physical Unclonable Functions based on NanoMOSFET Voltage DividerIn: 2015 AEIT International Annual Conference, Naples, Italy, 14-16 Oct. 2015,

[C25] Taco R, Levi I, Fish A, Lanuzza M (2014). Exploring back biasing opportunities in 28nm UTBB FD-SOI technology for subthreshold digital design. In: 2014 IEEE 28th Convention of Electrical & Electronics Engineers in Israel (IEEEI), Eilat, Israel, 3-5 Dec. 2014, pp. 1-4, ISBN: 978-1-4799-5987-7, doi: 10.1109/EEEI.2014.7005822

[C24] Lanuzza M, Taco R, Allbano D (2014). Dynamic gate-level body biasing for subthreshold digital design. In: 2014 IEEE 5th Latin American Symposium on Circuits and Systems (LASCAS). Santiago, Chile, 25-28 Feb. 2014, ISBN: 978-1-4799-2506-3, doi: 10.1109/LASCAS.2014.6820278

[C23] Lanuzza M, Taco R (2014). Improving speed and power characteristics of pulse-triggered flip-flops.  In: 2014 IEEE 5th Latin American Symposium on Circuits and Systems (LASCAS). Santiago, Chile, 25-28 Feb. 2014, ISBN: 978-1-4799-2506-3, doi: 10.1109/LASCAS.2014.6820287

[C22] Lanuzza M, De Rose R, Frustaci F, Perri S, Corsonello P (2011). Impact of process variations on pulsed flip-flops: Yield improving circuit-level techniques and comparative analysis. In: 20th International Workshop on Power and Timing Modeling, Optimization and Simulations (PATMOS). Grenoble, 7-10, September 2010, vol. 6448, pp. 180-189, ISBN: 3642177514, doi: 10.1007/978-3-642-17752-1-18

[C21] Kansal S, Lanuzza M, Corsonello P (2011). Self-repairing SRAM architecture to mitigate the inter-die process variations at 65nm technology. In: Proc. of SPIE – The International Society for Optical Engineering-VLSI Circuits and Systems V, vol. 8067, ISBN: 978-081948656-1, 7 pages, 3 May 2011, doi: 10.1117/12.886873

[C20] Frustaci F, Lanuzza M (2010). A New optimized high-speed low-power Data-Driven Dynamic (D3L) 32-bit Kogge-Stone adder. In: 19th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS). Delft, 9-11, September 2009, vol. 5953, pp. 357-366, ISBN: 3642118011, doi: 10.1007/978-3-642-11802-9_40

[C19] Lanuzza M, Zicari P, Frustaci F, Perri S, Corsonello P (2010). A Self-Hosting Configuration Management System to Mitigate the Impact of Radiation-Induced Multi-Bit Upsets in SRAM-Based FPGAs. In: IEEE International Symposium on Industrial Electronics (ISIE). Bari, 4-7 July 2010, ISBN: 978-142446391-6, doi: 10.1109/ISIE.2010.5637493

[C18] Frustaci F, Perri S, Lanuzza M, Corsonello P (2010). A new low-power high-speed single-clock-cycle binary comparator. In: Proc. of 2010 IEEE International Symposium on Circuits and Systems (ISCAS). Paris, 30 May-2 June 2010, p. 317-320, ISBN: 978-142445308-5, doi: 10.1109/ISCAS.2010.5537827

[C17] De Rose R, Lanuzza M, Frustaci F (2010). Design and evaluation of high-speed energy aware carry skip adders. In: Proc. of the 2010 International Conference on Microelectronics (ICM). Cairo, 19-22, December 2010, ISBN: 978-161284151-9, doi: 10.1109/ICM.2010.5696089

[C16] Lanuzza M, De Rose R, Frustaci F, Perri S, Corsonello P (2010). Impact of process variations on flip-flops energy and timing characteristics. In: Proc. of 2010 IEEE Annual Symposium on VLSI (ISVLSI). Lixouri, Kefalonia, 5-7, July 2010, ISBN: 978-076954076-4, doi: 10.1109/ISVLSI.2010.75

[C15] Kansal S, Lanuzza M, Corsonello P (2010). Impact of random process variations on different 65nm SRAM cell topologies. In: Proc. of the 3rd International Conference on Emerging Trends in Engineering and Technology (ICETET). p. 703-706, ISBN: 978-076954246-1, doi: 10.1109/ICETET.2010.19

[C14] Palumbo A, Calabrese B, Cocorullo G, Lanuzza M, Veltri P, Vizza P, Gambardella A, Sturniolo M (2009). A novel ICA-based hardware system for reconfigurable and portable BCI. In: 2009 IEEE International Workshop on Medical Measurements and Applications (MeMeA). Cetraro, 29-30, May 2009, p. 95-98, ISBN: 978-142443599-9, doi: 10.1109/MEMEA.2009.5167962

[C13] Lanuzza M, Zicari P, Frustaci F, Perri S, Corsonello P (2009). An efficient and low-cost design methodology to improve SRAM-Based FPGA robustness in space and avionics applications. In: 5th International Workshop of Applied Reconfigurable Computing (ARC). Karlsruhe, 16-18, March 2009, vol. 5453, p. 74-84, doi: 10.1007/978-3-642-00641-8_10

[C12] Purhoit S, Lanuzza M, Perri S, Corsonello P, Margala M (2009). Design Space Exploration of Energy-Delay-Area Efficient Coarse-Grain Reconfigurable Datapath. In: 22nd International Conference on VLSI Design – Held Jointly with 7th International Conference on Embedded Systems . New Delhi, India, 5-9 Gennaio 2009, p. 45-50, ISBN: 978-076953506-7, doi: 10.1109/VLSI.Design.2009.33

[C11] Lanuzza M, Perri S, Ccorsonello P, Margala M (2009). Energy efficient coarse-grain reconfigurable array for accelerating digital signal processing. In: 18th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS). Lisbon, September 10-12, 2008, vol. 5349 , p. 297-306, doi: 10.1007/978 3-540-95948-9_30

[C10] Purhoit S, Margala M, Lanuzza M, Corsonello P (2009). New Performance/Power/Area Efficient Reliable Full Adder Design. In: Proc. of the ACM Great Lakes Symposium on VLSI (GLSVLSI). Boston, MA, USA, 10/5/2009 – 12/5/2009, ISBN: 978-160558522-2, doi: 10.1145/1531542.153165

[C9] Cocorullo G, Corsonello P, De Nino M, Lanuzza M, Perri S, Staino G (2008). Design and Implementation of a Low Bit-Rate On-Board Satellite Wavelet-based Compression Core. In: On-Board Payload Data Compression Workshop 2008. Noordwijk, The Netherlands, 26 – 27 June 2008

[C8] Lanuzza M, Perri S, Corsonello P, Margala M (2007). A New Reconfigurable Coarse-Grain Architecture for Multimedia Applications. In: Proc. of 2007 NASA/ESA Conference on Adaptive Hardware and Systems (AHS). Edinburgh, 5-8 August, 2007, p. 119-126, ISBN: 978-076952866-3, doi: 10.1109/AHS.2007.10, (INVITED)

[C7] Corsonello P, Perri S, Staino G, Lanuzza M, Cocorullo G (2007). Design and Implementation of a 90nm low bit-rate image compression core. In: Proc. of 10th Euromicro Conference on Digital System Design Architectures, Methods and Tools (DSD). Lubeck, 29-31 Aug. 2007, p. 383-389, ISBN: 978-0-7695-2978-3, doi: 10.1109/DSD.2007.4341496

[C6] Lanuzza M, Perri S, Corsonello P (2007). MORA: A new coarse-grain reconfigurable array for high throughput multimedia processing. In: Proc. of 7th International Workshop on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS). Samos, 17-19, july 2007, vol. 4599, p. 159-168, ISBN: 978-354073622-6

[C5] Lanuzza M, Perri S, Corsonello P, Cocorullo G (2005). An efficient wavelet image encoder for FPGA-based design. In: Proc. of 2005 IEEE Workshop on Signal Processing Systems (SiPS): Design and Implementation. 2-4 Nov. 2005, p. 652-656, ISBN: 0-7803-9333-3, doi: 10.1109/SIPS.2005.1579946

[C4] Lanuzza M, Margala M, Corsonello P (2005). Cost-Effective Low-power Processor-In-Memory-based Reconfigurable datapath for Multimedia Applications. In: Proc. of the 2005 international symposium on Low power electronics and design (ISLPED). 8-10 Aug. 2005, p. 161-166, ISBN: 1-59593-137-6, doi: 10.1145/1077603.1077645

[C3] Lanuzza M, Perri S, Margala M, Corsonello P (2005). Low-Cost Fully Reconfigurable Data-Path for FPGA-Based Multimedia Processor. In: Proc. of 2005 International Conference on Field Programmable Logic and Applications (FPL). Tampere, 24-26 Aug. 2005, p. 13-18, ISBN: 978-078039362-2, doi: 10.1109/FPL.2005.1515692

[C2] Perri S, Lanuzza M , Corsonello P, Cocorullo G (2003). SIMD 2-D Convolver for Fast FPGA-based Image and Video Processors. In: Proc. of MAPLD 2003, Washington, USA, Sept. 2003.

[C1] Perri S, Lanuzza M, Corsonello P, Cocorullo G (2003). Fully-Synthesizable Reconfigurable Multiplier for High-Performance Multimedia Processors. In: Proc. of GSP International Signal Processing Conference, Dallas, USA, 2003.