International Journals

[J45] De Rose R, D’Aquino M, Finocchio G, Crupi F, Carpentieri M, Lanuzza M (2019). Compact Modeling of Perpendicular STT-MTJs with Double Reference Layers. IEEE TRANSACTIONS ON NANOTECHNOLOGY, ISSN: 1941-0085, vol. 18, issue 1, December 2019, pp. 1063 – 1070, doi: 10.1109/TNANO.2019.2945408

[J44] Garzon E, De Rose R , Crupi F,  Trojman L, Lanuzza M (2019). Assessment of STT-MRAM performance at nanoscaled technology nodes using a device-to-memory simulation framework. MICROELECTRONIC ENGINEERING, ISSN: 0167-9317, vol. 215, article number 111009,  July 2019, doi: 10.1016/j.mee.2019.111009

[J43] Taco R, Levi I, Lanuzza M, Fish A (2019). An 88-fJ/40-MHz [0.4V] – 0.61-pJ/1-GHz [0.9V] Dual-Mode Logic 8×8 bit Multiplier Accumulator With a Self-Adjustment Mechanism in 28-nm FD-SOI. IEEE JOURNAL OF SOLID STATE CIRCUITS, ISSN: 0018-9200, vol. 54, issue 2, February 2019, pp.  560 – 568, doi: 10.1109/JSSC.2018.2882139

[J42] De Rose R , Romero P, Lanuzza M (2019). Double-precision Dual Mode Logic Carry-Save Multiplier. INTEGRATION, the VLSI journal, ISSN: 0167-9260, vol. 64, January 2019, pp.  71–77, doi: 10.1016/j.vlsi.2018.08.003

[J41] Strangio S, Settino F, Palestri P, Lanuzza M, Crupi F, Esseni D, Selmi L (2018). Digital and analog TFET circuits: design and benchmark. SOLID-STATE ELECTRONICS, ISSN: 0038-1101, vol. 146, August 2018, pp.  50–65, doi: 10.1016/j.sse.2018.05.003, (INVITED Review)

[J40] Crupi F, De Rose R, Paliy M,  Lanuzza M, Perna M, Iannaccone G (2018). A Portable Class of 3-Transistor Current References with Low-Power Sub-0.5 V Operation. INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS, ISSN: 0098-9886,  vol. 46, issue 4, April 2018, pp. 779-795, doi: 10.1002/cta.2439 

[J39] De Rose R, Lanuzza M, Crupi F, Siracusano G, Tomasello R, Finocchio G, Carpentieri M,  Alioto M (2018). Variation-Aware Timing-Modeling Approach for Write Operation in Hybrid CMOS/STT-MTJ Circuits. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I,  ISSN: 1549-8328, vol. 65, iusse 3, March 2018, doi: 10.1109/TCSI.2017.2762431 (INVITED) 

[J38] Lanuzza M, Crupi F, Rao S, De Rose R, Iannaccone G (2017). Low Energy/Delay Overhead Level Shifter for Wide-Range Voltage Conversion. INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS, ISSN: 0098-9886, vol. 45, Issue 11, November 2017 , pp. 1637-1646, doi:  10.1002/cta.2294

[J37] Guerra N, De Rose R, Guevara M, Procel P, Lanuzza M, Crupi F (2017). Understanding the impact of point-contact scheme and selective emitter in a c-Si BC-BJ solar cell by full 3D numerical simulationsSOLAR ENERGY, ISSN: 0038-092X, vol. 155, October 2017, pp. 1443–1450, doi: 10.1016/j.solener.2017.07.051

[J36] De Rose R, Lanuzza M, d’Aquino M, Carangelo G, Finocchio G, Crupi F, Carpentieri M (2017). Compact Model with Spin-Polarization Asymmetry for Nanoscaled Perpendicular MTJs. IEEE TRANSACTIONS ON ELECTRON DEVICES,  ISSN: 0018-9383, vol. 64, issue 10, October 2017, pp. 43464353doi: 10.1109/TED.2017.2734967

[J35] Settino F, Lanuzza M, Strangio S, Crupi F, Palestri P, Esseni D, Selmi L (2017). Understanding the Potential and Limitations of Tunnel FETs for Low-Voltage Analog/Mixed-Signal Circuits. IEEE TRANSACTIONS ON ELECTRON DEVICES,  ISSN: 0018-9383, vol. 64, issue 6, June 2017, pp. 27362743doi: 10.1109/TED.2017.2689746

[J34] Procel P, Ingenito A, De Rose R, Pierro S, Crupi F, Lanuzza M, Cocorullo G, Isabella O, Zeman M (2017). Opto-electrical modelling and optimization study of a novel IBC c-Si  Solar Cell. PROGRESS IN PHOTOVOLTAICS: RESEARCH AND APPLICATIONS, ISSN: 1099-159X,  vol. 25, issue 6, June 2017, pp. 452–469,  doi:  10.1002/pip.2874

[J33] De Rose R, Lanuzza M,  Crupi F,  Siracusano G, Tomasello R, Finocchio G, Carpentieri M (2017).  Variability-Aware Analysis of Hybrid MTJ/CMOS Circuits by a Micromagnetic-Based Simulation Framework. IEEE TRANSACTIONS ON NANOTECHNOLOGY,  ISSN: 1941-0085, vol. 16, issue 2, March 2017, pp. 160-168, doi:  10.1109/TNANO.2016.2641681

[J32] De Rose R, Crupi F, Lanuzza M, Albano D (2017). A physical unclonable function based on a 2-transistor subthreshold voltage divider. INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS, vol. 45, issue 2, February 2017, pp. 260-273, ISSN: 0098-9886, doi:  10.1002/cta.2282

[J31] Strangio S, Palestri P, Lanuzza M,  Esseni D, Crupi F,  Selmi L (2017). Benchmarks of a III-V TFET technology platform against the 10-nm CMOS FinFET technology node considering basic arithmetic circuits. SOLID-STATE ELECTRONICS, ISSN: 0038-1101, vol. 128, February 2017, pp. 37–42, doi: 10.1016/j.sse.2016.10.022

[J30] Lanuzza M, Crupi F, Rao S, De Rose R, Strangio S, Iannaccone G (2017). An Ultra-Low Voltage Energy Efficient Level Shifter. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II, ISSN: 1549-7747, vol. 64, issue 1, January 2017, pp. 61-65, doi: 10.1109/TCSII.2016.2538724

[J29] Guevara M, Procel P, De Rose R, Guerra N, Crupi F, Lanuzza M (2016). Design guidelines for a metallization scheme with multiple-emitter contact lines in BC-BJ solar cells. JOURNAL OF COMPUTATIONAL ELECTRONICS, ISSN: 1569-8025,  vol 15, issue 4,  pp 1498–1504, December 2016, doi: 10.1007/s10825-016-0898-y

[J28] Strangio S, Palestri P, Lanuzza M,  Crupi F, Esseni D, Selmi L (2016). Assessment of InAs/AlGaSb Tunnel-FET Virtual Technology Platform for Low-Power Digital Circuits. IEEE TRANSACTIONS ON ELECTRON DEVICES, ISSN: 0018-9383, vol. 63, issue 7, pp. 2749-2756, doi:  10.1109/TED.2016.2566614

[J27] Taco R, Levi I,  Lanuzza M, Fish A (2016). Low Voltage Logic Circuits Exploiting Gate Level Dynamic Body Biasing in 28 nm UTBB FD-SOI. SOLID-STATE ELECTRONICS, Special Issue on PLANAR FULLY-DEPLETED SOI TECHNOLOGY, ISSN: 0038-1101, vol. 117, March 2016, pp. 185–192, doi: 10.1016/j.sse.2015.11.013

[J26] Lanuzza M, Strangio S, Crupi F, Palestri P, Esseni D (2015). Mixed Tunnel-FET/MOSFET Level Shifters: A New Proposal to Extend the Tunnel-FET Application Domain. IEEE TRANSACTIONS ON ELECTRON DEVICES, ISSN: 0018-9383, vol. 62, issue 12, pp. 3973–3979, doi: 10.1109/TED.2015.2494845

[J25] Albano D, Lanuzza M, Taco R, Crupi F (2015). Gate‐level body biasing for subthreshold logic circuits: analytical modeling and design guidelines. INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS, ISSN: 0098-9886, vol. 43, issue 11, pp. 1523–1540, doi: 10.1002/cta.2016

[J24] Finocchio G, Ricci M, Tomasello R, Giordano A, Lanuzza M, Puliafito V, Burrascano P, Azzerboni B, Carpentieri M (2015). Skyrmion based microwave detectors and harvesting. APPLIED PHYSICS LETTERS, ISSN: 00036951, vol. 107, issue 26, Article number 262401, doi: 10.1063/1.4938539

[J23] Taco R, Lanuzza M,  Albano D (2015). Ultra-low-Voltage Self-body-biasing Scheme and its Application to basic Arithmetic Circuits.  VLSI DESIGN, ISSN: 1065-514X, vol. 2015, Article ID 540482, pp. 1-10, doi: 10.1155/2015/540482

[J22] Lanuzza M, Corsonello P, Perri S (2015). Fast and Wide Range Voltage Conversion in Multisupply Voltage Designs. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, ISSN: 1063-8210, vol. 23, issue 2, pp. 388-391, doi: 10.1109/TVLSI.2014.2308400

[J21] Corsonello P, Frustaci F, Lanuzza M, Perri S (2014). Over/undershooting effects in accurate buffer delay model for sub-threshold domain. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I, vol. 61, issue 5, pp. 1456-1464, ISSN: 1549-8328, doi: 10.1109/TCSI.2013.2285691

[J20] Perri S, Lanuzza M, Corsonello P (2014). Design of High-Speed Low-Power Parallel-prefix adder trees in nanometer technologies. INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS, vol. 42, issue 7, pp. 731–743, ISSN: 0098-9886, doi: 10.1002/cta.1886

[J19] Frustaci F, Lanuzza M, Perri S, Corsonello P (2014). Analyzing noise robustness of wide fan-in dynamic logic gates under process variations. INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS, ISSN: 0098-9886, vol. 42, issue 5, pp. 452–467, ISSN: 0098-9886, doi: 10.1002/cta.1862

[J18] De Rose R, Lanuzza M, Frustaci F, Purhoit S (2014). Designing Dynamic Carry Skip Adders: Analysis and Comparison. CIRCUITS, SYSTEMS AND SIGNAL PROCESSING, vol. 33, issue 4, pp. 1019-1034, ISSN: 1531-5878, doi: 10.1007/s00034-013-9688-y

[J17] Corsonello P, Lanuzza M, Perri S (2014). Gate-level body biasing technique for high speed sub-threshold CMOS logic gates. INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS, vol. 42, issue 1, pp. 65-70, ISSN: 0098-9886, doi: 10.1002/cta.1838

[J16] Lanuzza M (2013). A Simple Circuit Approach to Improve Speed and Power Consumption in Pulse-Triggered Flip-Flops. JOURNAL OF LOW POWER ELECTRONICS, vol. 9, issue 4, pp. 445-451, ISSN: 1546-1998, doi:10.1166/jolpe.2013.1276

[J15] Magnone P, Tonini D, De Rose R, Frei M, Crupi F, Lanuzza M, Sangiorgi E, Fiegna C (2013). A Comparative Study of MWT Architectures by Means of Numerical Simulations. ENERGY PROCEDIA, vol. 38, pp. 131-136, ISSN:1876-6102, doi: 10.1016/j.egypro.2013.07.259 

[J14] Lanuzza M, Corsonello P, Perri S (2012). Low-Power Level Shifter for Multi-Supply Voltage Designs. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II, vol. 59, issue 12, pp.922-926, ISSN: 1549-7747, doi: 10.1109/TCSII.2012.2231037

[J13] Lanuzza M, De Rose R, Frustaci F, Perri S, Corsonello P (2012). Comparative analysis of yield optimized pulsed flip-flops. MICROELECTRONICS RELIABILITY, vol. 52, pp.1679-1689, ISSN: 0026-2714, doi: 10.1016/j.microrel.2012.03.024

[J12] Frustaci F, Perri S, Lanuzza M, Corsonello P (2012). Energy-efficient single-clock-cycle binary comparator. INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS, vol. 40, pp. 237-246, ISSN: 0098-9886, doi: 10.1002/cta.720

[J11] De Rose R, Van Wichelen K, Tous L, Das  J, Dross F, Fiegna  C, Lanuzza M, Sangiorgi E, Uruena De Castro  A , Zanuccoli M (2012). Optimization of Rear Point Contact Geometry by Means of 3-D Numerical Simulation. ENERGY PROCEDIA, vol. 27, pp. 197-202, ISSN:1876-6102, doi: 10.1016/j.egypro.2012.07.051

[J10] Lanuzza M, Frustaci F, Perri S, Corsonello P (2011). Design of Energy Aware Adder Circuits Considering Random Intra-Die Process Variations. JOURNAL OF LOW POWER ELECTRONICS AND APPLICATIONS, vol. 1, pp. 97-108, ISSN 2079-9268, doi: 10.3390/jlpea1010097, (INVITED) 

[J9] Purhoit S, Lanuzza M, Margala M (2010). Design Space Exploration of Split-Path Data Driven Dynamic Full Adder. JOURNAL OF LOW POWER ELECTRONICS,  vol. 6, issue 4, pp. 469-481, ISSN: 1546-1998, doi: 10.1166/jolpe.2010.1096

[J8] Lanuzza M, Zicari P, Frustaci F, Perri S, Corsonello P (2010). Exploiting Self Reconfiguration Capability to Improve SRAM-based FPGA Robustness in Space and Avionics Applications. ACM TRANSACTIONS ON RECONFIGURABLE TECHNOLOGY AND SYSTEMS, vol. 4, issue 1, article No 8, ISSN: 1936-7406, doi: 10.1145/1857927.1857935, (INVITED) 

[J7] Purhoit S, Lanuzza M, Perri S, Corsonello P, Margala M (2009). Design and evaluation of an energy-delay-area efficient datapath for coarse-grain reconfigurable computing systems. JOURNAL OF LOW POWER ELECTRONICS, vol. 5, issue 3, pp. 326-338, ISSN: 1546-1998, doi: 10.1166/jolpe.2009.1033, (INVITED) 

[J6] Frustaci F, Lanuzza M, Zicari P, Perri S, Corsonello P (2009). Designing High-Speed Adders in Power-Constrained Environments. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II, vol. 56, pp. 172-176, ISSN: 1549-7747, doi: 10.1109/TCSII.2008.2010187

[J5] Frustaci F, Lanuzza M, Zicari P, Perri S, Corsonello P (2009). Low-power split-path data driven dynamic logic. IET CIRCUITS, DEVICES & SYSTEMS, vol. 3, pp. 303-312, ISSN: 1751-858X, doi: 10.1049/iet-cds.2009.0099

[J4] Crupi F, Magnelli L, Falbo P, Lanuzza M, Nafria M, Rodriguez R (2007). Performance and reliability of ultra-thin oxide nMOSFETs under variable body bias. MICROELECTRONIC ENGINEERING, vol. 84, pp. 1947-1950, ISSN: 0167-9317, doi: 10.1016/j.mee.2007.04.015

[J3] Corsonello P, Perri S, Staino G, Lanuzza M, Cocorullo G (2006). Low bit rate image compression core for onboard space applications. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY, vol. 16, pp. 114-128, ISSN: 1051-8215, doi: 10.1109/TCSVT.2005.856925

[J2] Perri S, Lanuzza M, Corsonello P, Cocorullo G (2005). A high-performance fully reconfigurable FPGA-based 2D convolution processor. MICROPROCESSORS AND MICROSYSTEMS, Special Issue on FPGAs: Case Studies in Computer Vision and Image Processing, vol. 29, pp. 381-391, ISSN: 0141-9331, doi: 10.1016/j.micpro.2004.10.004

[J1] Perri S, Corsonello P, Iachino MA, Lanuzza M, Cocorullo G (2004). Variable precision arithmetic circuits for FPGA-based multimedia processors. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, vol. 12, pp. 995-999, ISSN: 1063-8210, doi: 10.1109/TVLSI.2004.833400