Alati A., Lanuzza M., Amendola G. Arnieri E. Boccia L. (2023), “Microstrip Gap Sensor for Dielectric Spectroscopy in Microfluidic Applications“, 2023 IEEE MTT-S International Microwave Biomedical Conference (IMBioC), Leuven, Belgium, 11-13 September 2023, doi: 10.1109/IMBioC56839.2023.10305114

Garzón E., Yavits L., Teman A., Lanuzza M. (2023), “STT-MRAM Technology For Energy-Efficient Cryogenic Memory Applications“, 2023 IEEE 14th Latin America Symposium on Circuits and Systems (LASCAS), Quito, Ecuador, 28 February 2023 – 03 March 2023, doi: 10.1109/LASCAS56464.2023.10108316

Hanhan R., Garzón E., Jahshan Z., Teman A., Lanuzza M., Yavits L. (2022), “EDAM: Edit Distance tolerant Approximate Matching content addressable memory“, 9th IEEE/ACM International Symposium on Computer Architecture, ISCA 2022, pp. 495-507, New York, USA, 18-22 June 2022, doi: 10.1145/3470496.3527424

Vatalaro M., De Rose R., Lanuzza M., Crupi F. (2022), “Stability-Area Trade-off in Static CMOS PUF Based on 4T Subthreshold Voltage Divider“, 29th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2022, Glasgow, 24-26 Oct. 2022, doi: 10.1109/ICECS202256217.2022.9970948

Garzon E., Golman R., Harel O., Noy T. , Kra Y., Pollock A., Yuzhaninov S., Shoshan Y., Rudin Y., Weitzman  Y. , Lanuzza M., Teman A. (2022), “A RISC-V-based Research Platform for Rapid Design Cycle“, IEEE International Symposium on Circuits and Systems, ISCAS 2022, Austin, Texas, USA, 27 May – 1 June 2022, doi: 10.1109/ISCAS48785.2022.9937866

Garzon E., Taco R., Procel L.M., Trojman L., Lanuzza M. (2022), “Voltage and Technology Scaling of DMTJ-based STT-MRAMs for Energy-Efficient Embedded Memories“,  IEEE 13th Latin American Symposium on Circuits and Systems, LASCAS 2022, Santiago, Chile, 1-4 March 2022,  doi: 10.1109/LASCAS53948.2022.9789054

Moposita T., Trojman L., Crupi F., Lanuzza M., Vladimirescu A.  (2022), “Voltage-to-Voltage Sigmoid Neuron Activation Function Design for Artificial Neural Networks“, IEEE 13th Latin American Symposium on Circuits and Systems, LASCAS 2022, Santiago, Chile, 1-4 March 2022,  doi: 10.1109/LASCAS53948.2022.9789075

Fassio L., Lin L., De Rose R., Lanuzza M.,  Crupi F., Alioto M. (2021), “A 3.2-pW, 0.2-V Trimming-Less Voltage Reference with 1.4-mV Across-Wafer Total Accuracy“, In: IEEE 47th European Solid State Circuits Conference (ESSCIRC 2021), Grenoble, France, 13-22 Sept. 2021, doi: 10.1109/ESSCIRC53450.2021.9567778

Felicetti C.,  Lanuzza M., Rullo A., Saccà D., Crupi F. (2021), “Exploiting Silicon Fingerprint for Device Authentication Using CMOS-PUF and ECC“, In: 2021 IEEE International Conference on Smart Internet of Things (SmartIoT), Jeju,  Republic of Korea, 13-15 Aug. 2021, doi: 10.1109/SmartIoT52359.2021.00043

Shavit N., Stanger I., Taco R., Lanuzza M., Fish A. (2021), “Live demonstration: A 0.8V, 1.54 pJ / 940 MHz dual mode logic-based 16×16-bit booth multiplier in 16-nm FinFET“, In: 2021 IEEE International Symposium on Circuits and Systems (ISCAS), Daegu, Korea, 22-28 May 2021, Article number 9401241, doi: 10.1109/ISCAS51556.2021.9401241

Stanger I., Shavit N., Taco R., Lanuzza M., Fish A. (2021), “Live Demo: Silicon evaluation of multimode dual mode logic for PVT-aware datapaths“, In: 2021 IEEE International Symposium on Circuits and Systems (ISCAS), Daegu, Korea, 22-28 May 2021, Article number 9401425, doi: 10.1109/ISCAS51556.2021.9401425

Escobar R., Prócel L.M., Trojman L., Lanuzza M., Taco R. (2021), “High-Speed and Low-Energy Dual-Mode Logic based Single-Cl0ck-Cycle Binary Comparator“, In: 2021 IEEE 12th Latin America Symposium on Circuits and System (LASCAS), Arequipa, Peru, 21-24 Feb. 2021, doi: 10.1109/LASCAS51355.2021.9459151

Trojman L., Rivadeneira D., Villegas M., Acurio E., Lanuzza M.,  Prócel L.M., Taco R. (2021), “RF-DC Multiplier for RF Energy Harvester based on 32nm and TFET technologies“, In: 2021 IEEE 12th Latin America Symposium on Circuits and System (LASCAS), Arequipa, Peru, 21-24 Feb. 2021, doi: 10.1109/LASCAS51355.2021.9459129

Vicuna K., Mosquera C., Redon M., Musello A., Lanuzza M., Procel L.M., Taco R., Trojman L. (2021), ” A 180 nm Low-Cost Operational Amplifier for IoT Applications“, In: ETCM 2021 – 5th Ecuador Technical Chapters Meeting, Cuenca, Ecuador, 12-15 Oct. 2021, pp. 1-4, doi: 10.1109/ETCM53643.2021.9590655

Stanger I., Shavit N., Taco R., Yavits L., Lanuzza M., Fish A. (2020), “Robust Dual Mode Pass Logic (DMPL) for Energy Efficiency and High Performance“, In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), Sevilla, Spain, 10-21 Oct.  2020, pp. 1-4, doi: 10.1109/ISCAS45731.2020.9181127

Taco R., Yavits L.,  Shavit N., Stanger I., Lanuzza M., Fish A. (2020),”Exploiting Single-Well Design for Energy-Efficient Ultra-Wide Voltage Range Dual Mode Logic-Based Digital Circuits in 28nm FD-SOI Technology“, In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), Sevilla, Spain, 10-21 Oct.  2020, pp. 1-4, doi: 10.1109/ISCAS45731.2020.9180449

Fassio L., Lin L., De Rose R., Lanuzza M.,  Crupi F., Alioto M. (2020), ” A 0.25-V, 5.3-pW Voltage Reference with 25-μV/°C Temperature Coefficient, 140-μV/V Line Sensitivity and 2,200-μm² Area in 180nm“, In: 2020 IEEE Symposium on VLSI Circuits, Honolulu, HI, USA, USA, 16 – 19 June 2020, doi: 10.1109/VLSICircuits18222.2020.9162872

Lanuzza M, De Rose R , Garzon E, Crupi F (2019).Evaluating the Energy Efficiency of STT-MRAMs Based on Perpendicular MTJs with Double Reference Layers. In: 2019 IEEE 13th International Conference on ASIC (ASICON), Chongqing, China, 29 Oct. – 1 Nov. 2019, doi: 10.1109/ASICON47005.2019.8983643, (INVITED)

Garzon E, De Rose R , Crupi F, Lanuzza M (2019). Device-to-System Level Simulation Framework for STT-DMTJ Based Cache Memory. In: 26th IEEE International Conference on Electronics, Circuits and Systems (ICECS), Genova, Italy, 27-29 Nov. 2019, doi: 10.1109/ICECS46596.2019.8965021

Lanuzza M, De Rose R , Crupi F, Alioto M (2019). An Energy Aware Variation-Tolerant Writing Termination Control for STT-based Non Volatile Flip-Flops. In: 26th IEEE International Conference on Electronics, Circuits and Systems (ICECS), Genova, Italy, 27-29 Nov. 2019, doi: 10.1109/ICECS46596.2019.8964742

Garzon E, De Rose R , Crupi F,  Trojman L, Finocchio G, Carpentieri M, Lanuzza M (2019). Exploiting Double-Barrier MTJs for Energy-Efficient Nanoscaled STT-MRAMs. In: 16th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), Lausanne, Switzerland, 15 -18 July 2019, pp. 1-4, doi: 10.1109/SMACD.2019.8795223

Taco R, Levi I, Lanuzza M, Fish A (2019). Live demo: An 88-fJ/40-MHz [0.4V] – 0.61-pJ/1-GHz [0.9V] Dual-Mode Logic 8×8 bit Multiplier Accumulator With a Self-Adjustment Mechanism in 28-nm FD-SOI. In: 2019 IEEE International Symposium on Circuits and Systems (ISCAS), Sapporo, Japan, 26-29 May 2019, doi: 10.1109/ISCAS.2019.8702170

De Rose R, Crupi F,  Paliy M,  Lanuzza M, Iannaccone G (2018). Design of a 3T current reference for low-voltage, low-power operation. In: 2018 International Conference on IC Design & Technology (ICICDT),  Otranto, Italy, 4-6 June 2018, pp. 1-4, doi: 10.1109/ICICDT.2018.8399744

Guerra N, De Rose R, Guevara M, Procel P, Lanuzza M, Crupi F (2018). Impact of the Emitter Contact Pattern in c-Si BC- BJ Solar Cells by Numerical Simulations. In:  2018 IEEE 4th International Forum on Research and Technology for Society and Industry (RTSI), Palermo, Italy, 10-13 Sept. 2018, pp. 1-4, doi: 10.1109/RTSI.2018.8548423

Taco R, Levi I, Lanuzza M, Fish A (2017). Energy-delay tradeoffs of low-voltage dual mode logic in 28nm FD-SOI. In: 2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), Burlingame, CA, USA, 16-19 October 2017, pp. 1-3, doi: 10.1109/S3S.2017.8309250

Settino F, Strangio S, Lanuzza M, Crupi F, Palestri P, Esseni D (2017).Simulations and comparisons of basic analog and digital circuit blocks employing Tunnel FETs and conventional FinFETs. In: 2017 Fifth Berkeley Symposium on Energy Efficient Electronic Systems & Steep Transistors Workshop (E3S), Berkeley, CA, USA, 19-20 October 2017, pp.  1-3, doi: 10.1109/E3S.2017.8246154

De Rose R, Crupi F,  Albano D,  Lanuzza M (2017). Design of a sub-1 V nanopower CMOS current Reference. In: 2017 European Conference on Circuit Theory and Design (ECCTD), Catania, Italy, 4-6 Sept. 2017, pp. 1-4, doi: 10.1109/ECCTD.2017.8093351

De Rose R, Carangelo G,  Lanuzza M,  Crupi F,  Finocchio G, Carpentieri M (2017). Impact of voltage scaling on STT-MRAMs through a variability-aware simulation framework. In: 2017 14th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), Giardini Naxos – Taormina, Italy, 12-15 June 2017, pp. 1-4, doi: 10.1109/SMACD.2017.7981583

Settino F, Lanuzza M, Strangio S, Crupi F,  Palestri P, Esseni D (2017). A virtual III-V tunnel FET technology platform for ultra-low voltage comparators and level shifters. In: 2017 13th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME), Giardini Naxos – Taormina, Italy, 12-15 June 2017, pp. 145-148, doi:  10.1109/PRIME.2017.7974128

Taco R, Levi I, Lanuzza M, Fish A (2017). Evaluation of Dual Mode Logic in 28nm FD-SOI technology. In: 2017 IEEE International Symposium on Circuits and Systems (ISCAS), Baltimore, MD, USA, 28-31 May 2017, pp. 1-4, doi: 10.1109/ISCAS.2017.8050998

De Rose R, Lanuzza M, Crupi F, Siracusano G, Tomasello R, Finocchio G, Carpentieri M, Alioto M (2017). A variation-aware simulation framework for hybrid CMOS/spintronic circuits. In: 2017 IEEE International Symposium on Circuits and Systems (ISCAS), Baltimore, MD, USA, 28-31 May 2017, pp. 1-4, doi: 10.1109/ISCAS.2017.8050920

Crupi F, Strangio S, Palestri P, Lanuzza M, Esseni D (2016). Early Assessment of Tunnel-FET for Energy-Efficient Logic Circuits. In: 2016 IEEE 13th International Conference  on Solid-State and Integrated Circuit Technology (ICSIT), Hangzhou, China, 25-28 Oct. 2016,  pp. 27 – 30, doi: 10.1109/ICSICT.2016.7998830, (INVITED)

Taco R, Levi I, Lanuzza M, Fish A (2016). Extended Exploration of Low Granularity Back Biasing Control in 28nm UTBB FD-SOI Technology. In: 2016 IEEE International Symposium on Circuits and Systems (ISCAS),  Montreal, Canada, 22-25 May 2016, pp. 41-44, doi: 10.1109/ISCAS.2016.7527165

Strangio S, Palestri P, Lanuzza M, Esseni D, Crupi F, Selmi L (2016). Benchmarks of a III-V TFET technology platform against the 10-nm CMOS technology node considering 28T Full-Adders. In: 2016 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS), Vienna, Austria, 25-27 Jan. 2016, pp. 139 – 142, doi: 10.1109/ULIS.2016.7440072 

Taco R, Levi I, Lanuzza M, Fish A (2015). Low voltage Ripple Carry Adder with low-Granularity Dynamic Forward Back-Biasing in 28 nm UTBB FD-SOI. In: IEEE SOI-3D-Subthreshold (S3S) Microelectronics Technology Unified Conference, San Francisco (CA), USA, 5-8 Oct. 2015,  pp. 1-2, doi: 10.1109/S3S.2015.7333515

Cordopatri A, De Rose R, Felicetti C, Lanuzza M, Cocorullo G (2015). Hardware implementation of a Test Lab for Smart Home environments. In: 2015 AEIT International Annual Conference, Naples, Italy, 14-16 Oct. 2015, pp. 1 – 6, doi: 10.1109/AEIT.2015.7415221

Crupi F, Albano D, Lanuzza M (2015). Physical Unclonable Functions based on NanoMOSFET Voltage Divider. In: 2015 AEIT International Annual Conference, Naples, Italy, 14-16 Oct. 2015,

Taco R, Levi I, Fish A, Lanuzza M (2014). Exploring back biasing opportunities in 28nm UTBB FD-SOI technology for subthreshold digital design. In: 2014 IEEE 28th Convention of Electrical & Electronics Engineers in Israel (IEEEI), Eilat, Israel, 3-5 Dec. 2014, pp. 1-4, ISBN: 978-1-4799-5987-7, doi: 10.1109/EEEI.2014.7005822

Lanuzza M, Taco R, Allbano D (2014). Dynamic gate-level body biasing for subthreshold digital design. In: 2014 IEEE 5th Latin American Symposium on Circuits and Systems (LASCAS). Santiago, Chile, 25-28 Feb. 2014, ISBN: 978-1-4799-2506-3, doi: 10.1109/LASCAS.2014.6820278

Lanuzza M, Taco R (2014). Improving speed and power characteristics of pulse-triggered flip-flops.  In: 2014 IEEE 5th Latin American Symposium on Circuits and Systems (LASCAS). Santiago, Chile, 25-28 Feb. 2014, ISBN: 978-1-4799-2506-3, doi: 10.1109/LASCAS.2014.6820287

Lanuzza M, De Rose R, Frustaci F, Perri S, Corsonello P (2011). Impact of process variations on pulsed flip-flops: Yield improving circuit-level techniques and comparative analysis. In: 20th International Workshop on Power and Timing Modeling, Optimization and Simulations (PATMOS). Grenoble, 7-10, September 2010, vol. 6448, pp. 180-189, ISBN: 3642177514, doi: 10.1007/978-3-642-17752-1-18

Kansal S, Lanuzza M, Corsonello P (2011). Self-repairing SRAM architecture to mitigate the inter-die process variations at 65nm technology. In: Proc. of SPIE – The International Society for Optical Engineering-VLSI Circuits and Systems V, vol. 8067, ISBN: 978-081948656-1, 7 pages, 3 May 2011, doi: 10.1117/12.886873

Frustaci F, Lanuzza M (2010). A New optimized high-speed low-power Data-Driven Dynamic (D3L) 32-bit Kogge-Stone adder. In: 19th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS). Delft, 9-11, September 2009, vol. 5953, pp. 357-366, ISBN: 3642118011, doi: 10.1007/978-3-642-11802-9_40

Lanuzza M, Zicari P, Frustaci F, Perri S, Corsonello P (2010). A Self-Hosting Configuration Management System to Mitigate the Impact of Radiation-Induced Multi-Bit Upsets in SRAM-Based FPGAs. In: IEEE International Symposium on Industrial Electronics (ISIE). Bari, 4-7 July 2010, ISBN: 978-142446391-6, doi: 10.1109/ISIE.2010.5637493

Frustaci F, Perri S, Lanuzza M, Corsonello P (2010). A new low-power high-speed single-clock-cycle binary comparator. In: Proc. of 2010 IEEE International Symposium on Circuits and Systems (ISCAS). Paris, 30 May-2 June 2010, p. 317-320, ISBN: 978-142445308-5, doi: 10.1109/ISCAS.2010.5537827

De Rose R, Lanuzza M, Frustaci F (2010). Design and evaluation of high-speed energy aware carry skip adders. In: Proc. of the 2010 International Conference on Microelectronics (ICM). Cairo, 19-22, December 2010, ISBN: 978-161284151-9, doi: 10.1109/ICM.2010.5696089

Lanuzza M, De Rose R, Frustaci F, Perri S, Corsonello P (2010). Impact of process variations on flip-flops energy and timing characteristics. In: Proc. of 2010 IEEE Annual Symposium on VLSI (ISVLSI). Lixouri, Kefalonia, 5-7, July 2010, ISBN: 978-076954076-4, doi: 10.1109/ISVLSI.2010.75

Kansal S, Lanuzza M, Corsonello P (2010). Impact of random process variations on different 65nm SRAM cell topologies. In: Proc. of the 3rd International Conference on Emerging Trends in Engineering and Technology (ICETET). p. 703-706, ISBN: 978-076954246-1, doi: 10.1109/ICETET.2010.19

Palumbo A, Calabrese B, Cocorullo G, Lanuzza M, Veltri P, Vizza P, Gambardella A, Sturniolo M (2009). A novel ICA-based hardware system for reconfigurable and portable BCI. In: 2009 IEEE International Workshop on Medical Measurements and Applications (MeMeA). Cetraro, 29-30, May 2009, p. 95-98, ISBN: 978-142443599-9, doi: 10.1109/MEMEA.2009.5167962

Lanuzza M, Zicari P, Frustaci F, Perri S, Corsonello P (2009). An efficient and low-cost design methodology to improve SRAM-Based FPGA robustness in space and avionics applications. In: 5th International Workshop of Applied Reconfigurable Computing (ARC). Karlsruhe, 16-18, March 2009, vol. 5453, p. 74-84, doi: 10.1007/978-3-642-00641-8_10

Purhoit S, Lanuzza M, Perri S, Corsonello P, Margala M (2009). Design Space Exploration of Energy-Delay-Area Efficient Coarse-Grain Reconfigurable Datapath. In: 22nd International Conference on VLSI Design – Held Jointly with 7th International Conference on Embedded Systems . New Delhi, India, 5-9 Gennaio 2009, p. 45-50, ISBN: 978-076953506-7, doi: 10.1109/VLSI.Design.2009.33

Lanuzza M, Perri S, Corsonello P, Margala M (2009). Energy efficient coarse-grain reconfigurable array for accelerating digital signal processing. In: 18th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS). Lisbon, September 10-12, 2008, vol. 5349 , p. 297-306, doi: 10.1007/978 3-540-95948-9_30

Purhoit S, Margala M, Lanuzza M, Corsonello P (2009). New Performance/Power/Area Efficient Reliable Full Adder Design. In: Proc. of the ACM Great Lakes Symposium on VLSI (GLSVLSI). Boston, MA, USA, 10/5/2009 – 12/5/2009, ISBN: 978-160558522-2, doi: 10.1145/1531542.153165

Cocorullo G, Corsonello P, De Nino M, Lanuzza M, Perri S, Staino G (2008). Design and Implementation of a Low Bit-Rate On-Board Satellite Wavelet-based Compression Core. In: On-Board Payload Data Compression Workshop 2008. Noordwijk, The Netherlands, 26 – 27 June 2008

Lanuzza M, Perri S, Corsonello P, Margala M (2007). A New Reconfigurable Coarse-Grain Architecture for Multimedia Applications. In: Proc. of 2007 NASA/ESA Conference on Adaptive Hardware and Systems (AHS). Edinburgh, 5-8 August, 2007, p. 119-126, ISBN: 978-076952866-3, doi: 10.1109/AHS.2007.10, (INVITED)

Corsonello P, Perri S, Staino G, Lanuzza M, Cocorullo G (2007). Design and Implementation of a 90nm low bit-rate image compression core. In: Proc. of 10th Euromicro Conference on Digital System Design Architectures, Methods and Tools (DSD). Lubeck, 29-31 Aug. 2007, p. 383-389, ISBN: 978-0-7695-2978-3, doi: 10.1109/DSD.2007.4341496

Lanuzza M, Perri S, Corsonello P (2007). MORA: A new coarse-grain reconfigurable array for high throughput multimedia processing. In: Proc. of 7th International Workshop on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS). Samos, 17-19, july 2007, vol. 4599, p. 159-168, ISBN: 978-354073622-6

Lanuzza M, Perri S, Corsonello P, Cocorullo G (2005). An efficient wavelet image encoder for FPGA-based design. In: Proc. of 2005 IEEE Workshop on Signal Processing Systems (SiPS): Design and Implementation. 2-4 Nov. 2005, p. 652-656, ISBN: 0-7803-9333-3, doi: 10.1109/SIPS.2005.1579946

Lanuzza M, Margala M, Corsonello P (2005). Cost-Effective Low-power Processor-In-Memory-based Reconfigurable datapath for Multimedia Applications. In: Proc. of the 2005 international symposium on Low power electronics and design (ISLPED). 8-10 Aug. 2005, p. 161-166, ISBN: 1-59593-137-6, doi: 10.1145/1077603.1077645

Lanuzza M, Perri S, Margala M, Corsonello P (2005). Low-Cost Fully Reconfigurable Data-Path for FPGA-Based Multimedia Processor. In: Proc. of 2005 International Conference on Field Programmable Logic and Applications (FPL). Tampere, 24-26 Aug. 2005, p. 13-18, ISBN: 978-078039362-2, doi: 10.1109/FPL.2005.1515692

Perri S, Lanuzza M , Corsonello P, Cocorullo G (2003). SIMD 2-D Convolver for Fast FPGA-based Image and Video Processors. In: Proc. of MAPLD 2003, Washington, USA, Sept. 2003.

Perri S, Lanuzza M, Corsonello P, Cocorullo G (2003). Fully-Synthesizable Reconfigurable Multiplier for High-Performance Multimedia Processors. In: Proc. of GSP International Signal Processing Conference, Dallas, USA, 2003.